Electronic component and method for measuring its qualification

ABSTRACT

The invention relates to an electronic component with an integrated semiconductor circuit that comprises a core with functional flip-flops. A part of the functional flip-flops is linked as input flip-flops with input pins of the component and a part of the functional flip-flops is linked as output flip-flops with output pins of the component. In order to allow for efficient and cost-effective ASIC qualification methods that can be carried out rapidly and that take into consideration the growing complexity of integrated circuits and the rapid development of technology, the invention provides a method and a device wherein the input flip-flops and the output flip-flops are interconnected to a shift register during a qualification measurement of the component.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Stage of International ApplicationNo. PCT/EP02/09689, filed Aug. 30, 2002 and claims the benefit thereof.The International Application claims the benefits of Europeanapplication No. 01122773.3 filed Sep. 21, 2001, both applications areincorporated by reference herein in their entirety.

FIELD OF INVENTION

The invention relates to an electronic component with integratedsemiconductor circuit that comprises a core containing functionalflip-flops, some of the functional flip-flops being connected as inputFFs to input pins of the component, and some of the functionalflip-flops being connected as output FFs to output pins of thecomponent, as well as a method for its qualification testing.

BACKGROUND OF INVENTION

Electrical components of this type are often designed as ApplicationSpecific Integrated Circuits (ASICs), which undergo extensivequalification procedures after fabrication. ASICs are a collection ofcircuits having simple functions, such as flip-flops, inverters, NANDsand NORs, and of more complex structures such as memory arrays, adders,counters and phase locked loops. The various circuits are combined in anASIC in order to implement a specific application. ASICs are used innumerous products, for instance consumer products such as video games,digital cameras, in vehicles and PCs and also in high-end technologyproducts such as workstations and supercomputers.

Known ASIC architectures comprise an ASIC are containing the variouscircuit elements making up the function of the ASIC. The ASIC corereceives the inputs to be processed from input drivers. After processingby the ASIC core, the output data is output via output drivers.

Various “Design for Test” (DFT) techniques are known for testing thefunctionality of the ASIC. The advantage of DFT techniques is thatcircuit elements can be inserted back at the chip design stage, whichenables later scanbased testing and reduces the number of test pointsrequired on the ASIC board while also getting around the problem ofunavailable access points.

Large numbers of test vectors are created in known qualification methodsor test methods. These test vectors are then input into an ASIC, the aimbeing to drive certain outputs of the ASIC in order to change thelogical state. When the output state changes, the “clock-to-outputdelay” can be measured, giving the delay between the supplied clockingpulse and the output appearing at the output. For the input areas of anASIC, qualification methods are used to determine any timing violationthat may exist, e.g. violation of the SETUP and HOLD time (see below),and to signal it at the output of the ASIC.

For the output of a flip-flop to be determinate, i.e. not metastable,the inputs to the flip-flop must lie within the SETUP and HOLD timespecification for the flip-flop. The SETUP time is the time period priorto the rising edge of the synchronization clock. The HOLD time refers tothe time period after the rising edge of the synchronization clock. Ifthe SETUP and HOLD timing criteria of the flip-flop are not met, theoutput of the flip-flop is not definitely guaranteed. Thus it isextremely important to find the SETUP and HOLD time accurately.

Considerable amounts of time are involved in creating test vectors forqualification methods described above, because some of the test vectorsare generated by hand. In addition, it is necessary to know the functionof the ASIC core.

Furthermore, the requirements of the test setup must be met, i.e. itmight be necessary to stop the test run in order to reload the testvectors because of limited memory depth.

Factors such as high pin count, complexity or logic depth, internalphase locked loops (PLLS) and logic power-up sequences of the ASIC alsopresent problems for the test methods used for qualification of theASIC. These factors will present even greater difficulties for ASICqualification in the future.

SUMMARY OF INVENTION

It is thus the object of the invention stated in claim 1 to create anelectronic component and demonstrate a qualification method that in eachcase provide an efficient, cost-effective and quick to perform ASICqualification method, while at the same time taking into account theever increasing complexity of integrated circuits and the acceleratingdevelopment pace of technology.

This object is achieved by an electronic component as claimed in claim1, in which the input FFs and the output FFs can be connected togetherinto a shift register during a qualification test of the component.

This results in the following advantages:

-   -   Only relatively short test vectors need to be used for the        timing measurement.    -   Short test times are obtained irrespective of the logic depth of        the ASIC under test.    -   The test vectors can be generated automatically from a database        similar to the Boundary Scan Description Language file (BDSL        File).    -   Test teams need to get far less involved than before in the        function of the ASIC.

According to another advantageous embodiment of the present invention,the input FFs and the output FFs each have a switching element at theirinputs, and are connected together by means of these under control froma controller central to all the switching elements. This reducesconsiderably the time involved in preparing timing measurements on theASIC.

In a particularly advantageous embodiment, the qualification test is asetup and/or a hold measurement at the input FFs, by means of which thetiming measurements can be made without needing to put the central coreinto operation, and specific inputs and outputs of the integratedcircuit are measured using test vectors irrespective of the logic depthin order to be able to make a setup and hold time measurement at theinputs.

In a further advantageous embodiment, the qualification test is aclock-to-output time measurement at the output FFs and/or the outputs ofthe component, by means of which the timing measurements can be madewithout needing to put the central core into operation, and specificoutputs of the integrated circuit are measured using test vectorsirrespective of the logic depth in order to be able to find theclock-to-output delay at the outputs.

In another preferred exemplary embodiment of the invention, thequalification test is an enable-to-output time measurement at the outputFFs (8) and/or the outputs of the component (1), by means of which theswitching speed of the tristate buffers can be measured.

In another advantageous embodiment, the switching elements aremultiplexers, which means that only a small amount of overhead isrequired in the hardware.

In another advantageous exemplary embodiment, during the qualificationtest, the respective switching elements connect the output of one inputFF or output FF to the input of an adjacent input FF or output FFrespectively, in order to produce the shift register in a particularlysimple way.

In another advantageous exemplary embodiment, all input and output FFsreceive the same clock via a clock tree during the qualification test.Thus a real clock is present during the timing measurements, and theclock tree relevant to the test and the PLLs are included in the timingmeasurements.

In another advantageous exemplary embodiment, the input and/or outputFFs receive a different clock via a clock tree in order to providequalification tests for an ASIC having different clock domains.

In a particularly advantageous exemplary embodiment, the controller hasa first pin for controlling the switching elements, a second pin forcontrolling the unidirectional output buffers and a third pin forcontrolling the bidirectional output buffers, in order to provide theshift register and the control of the output buffers during thequalification test separately or in addition to the control from othertest methods such as the production test, or a control from the coreitself.

In an alternative advantageous exemplary embodiment, the controller hasa multiplicity of gates in order to provide, during the qualificationmethod according to the invention, masking of controls from other testprocedures, such as the production test, or of a control from the coreitself.

In achieving the object according to the invention by providing a methodfor qualification testing of an electrical component as claimed in claim13, in which the input FFs and output FFS are connected together into ashift register during a qualification test of the component, the sameadvantages result as for the device described above.

An exemplary embodiment of the method according to the invention, inwhich the test data is input in parallel to the input FFS via inputs ofthe component, and then the controller connects together the input FFsand the output FFs into the shift register, whereby the test data passesserially through the shift register and is read out via one output,results in the additional advantage that timing measurements in theinput area can be performed without needing to put the central core intooperation.

In another exemplary embodiment of the method according to theinvention, the setup and hold time is found by varying the timing of thedata input to the input FFs relative to the clock and by verifying thetest data read out, enabling a precise definition of the setup and holdcriteria to be found.

In another additional exemplary embodiment of the method according tothe invention, the controller connects the input FFs and the output FFSinto a shift register, the test data is input serially into an input FFvia an input of the component, the test data reaches the output FFS bypassing serially through the shift register, and the clock-to-outputtimes are measured at the relevant outputs of the component during theshifting sequence of the data into the output FFS. This results in theadditional advantage that timing measurements can be made in the outputarea without needing to put the central core into operation.

In a particularly advantageous exemplary embodiment of the methodaccording to the invention, the test data is input in parallel into theinput FFs via the inputs of the component, the controller then connectsthe input FFs and the output FFs into a shift register, the test datareaches the output FFs by passing serially through the shift register,and the clock-to-output times is measured at the relevant outputs of thecomponent during the shifting sequence of the data into the output FFs.This allows a timing measurement to be made particularly quickly in theoutput area of the ASIC without needing to put the central core intooperation.

In another advantageous exemplary embodiment of the method according tothe invention, a tristate buffer is controlled by a flip-flop (8 d) ofthe shift register during the enable-to-output time measurement in theoutput area, the test vector data input serially into the shift registerbeing used for the control. This enables an enable-to-output timemeasurement that is particularly simple to implement.

BRIEF DESCRIPTION OF THE DRAWING

An exemplary embodiment of the invention is shown in the drawing and isdescribed in more detail below. The single figure of the applicationshows a schematic diagram of an electronic component according to thepresent invention.

DETAILED DESCRIPTION OF INVENTION

FIG. 1 shows an electronic component, more precisely an ApplicationSpecific Integrated Circuit (ASIC) 1 containing an integrated circuit(IC). The IC comprises an ASIC core 2 containing circuit elements suchas flip-flops, inverters, NANDs and NORs etc. The arrangement of thecircuit elements in the ASIC core 2 provides the specific function ofthe ASIC 1.

The data to be processed by the ASIC core 2 is input to the ASIC core 2in parallel via input pins 3 a, 3 b, 3 c and respective series-connectedinput buffers 4 a, 4 b, 4 c, 4 d.

After processing by the ASIC core 2, the processed data is output inparallel via unidirectional tristate buffers 5 a, 5 b, 5 c andrespective output pins 6 a, 6 b and 6 c. The tristate output buffers 5a, 5 b, 5 c can assume the logic states 1 and 0 and a high impedancestate Z. In the preferred exemplary embodiment of the present invention,at least one pin 6 a is bidirectional, i.e. the pin 6 a can be used asan input pin via the input buffer 4 d by switching of the tristatebuffer 5 a into the Z state.

In the ASIC core 2 there are corresponding input flip-flops (input FFs)7 a, 7 b, 7 d and corresponding output flip-flops (output FFs) 8 a, 8 b,8 c, 8 d for the respective input and output pins 3, 6. The input FFs 7a, 7 b, 7 d are arranged in at least one input block 9, and the outputFFs 8 a, 8 b, 8 d are arranged in at least one output block 10. The ASICcore 2 is thus divided into at least three blocks: the input block 9,the output block 10 and a central core 11. The input block 9 and theoutput block 10 together form the part of the core 2 referred to as thecore boundary.

The circuit elements of the input block 9, the output block 10 and thecentral core 11 together provide the function of the IC of the ASIC 1.The circuit elements are functional flip-flops (FF) and other functionalelements such as inverters, NANDs and NORs etc. The term “functional” isused below to refer to flip-flops or other circuit elements that areonly needed for operating the ASIC 1 and for implementing itsapplication-specific function. Such flip-flops or circuit elements thatare additionally provided e.g. solely and exclusively for performingtest procedures are not covered by this term.

In normal operation of the ASIC 1, the data is input via the input pins3, and clocked in parallel into the input FFs 7 a, 7 b, 7 d of the inputblock 9. The data is then transferred in parallel into the central core11 and processed further. After processing in the central core 11, thedata is passed in parallel into the output block 10 where the data isclocked into the output FFs 8 a, 8 b, 8 d and transferred to the outputpins 6 a, 6 b and 6 c.

The ASIC 1 has a clock input 12 that clocks the ASIC core 2 via a clocktree 13. The central core 11 and the blocks 9,10 are clocked by usingsuitable phase locked loops (PLLs) or delay elements (clock input forcentral core not shown). Each input FF 7 a, 7 b, 7 d and each output FF8 a, 8 b, 8 d is clocked via clock pins 14 and clock lines 15.

To perform a timing measurement in the input areas and the output areasof the ASIC 1, the input FFs 7 a, 7 b, 7 d are configured with theoutput FFs 8 a, 8 b, 8 d into a shift register. This is made possible bythe series connection of multiplexers 16 to the respective input of aninput FF or output FF 7,8. In normal operation of the ASIC 1, themultiplexer 16 switches the inputs from the input pins 3 a, 3 b, 3 c andthe outputs from the central core 11 into the input and output FFs 7,8respectively.

During the ASIC timing measurement, the multiplexers 16 connect theinput FFs and output FFs together via lines 17 into a shift register, ormore precisely a scan chain (Core Boundary Scan). The chain starts atthe input pin 3 c, which becomes the input pin TESTER_IN for the testprocedure, and ends at the last output FF 8 c of an output 6 c thatdoubles as TESTER_OUT.

The multiplexers 16 may already be present for performing the productiontest along a scan path. In the production test, the functionality ofcircuit elements in the ASIC core 2 is tested along scan paths or testpaths.

The ASIC 1 is switched into the shift mode in the same way as for theproduction test via a SCAN_ENABLE pin 18 that forms part of a testcontroller 28. The controller 28, also referred to as a combinatorialdevice, controls switching elements of the ASIC core 2 and theunidirectional and bidirectional buffers 5 a, 5 b and 5 c whenqualification procedures are being performed on the ASIC.

When the shift register is meant to be formed, the multiplexers 16 arecontrolled by a signal applied to the SCAN_ENABLE pin 18 via scan lines19. Since the SCAN_ENABLE pin is also used for the production test,signals applied to the pin 18 are also fed to other sections (not shown)of the ASIC core 2 via a multiplexer 20 of the controller 28, saidmultiplexer being controlled by a scan-mode pin 21 assigned to thecontroller 28. This is done in order to connect “scan paths”, or testpaths, for the production test in the core 2. It would also be possible,however, to input control data from a built-in self-test controller(BIST controller) 21 into the core 2 via the multiplexer 20.

The controller 28 has a TESTER_ENABLE pin 23 a for controlling theunidirectional tristate output buffers 5 a, 5 b, 5 c. The signal fromthe TESTER_ENABLE pin 23 a is input with any control signals presentfrom the core into a first gate 25 of the controller 28. In thepreferred exemplary embodiment, the first gate 25 is an AND gate, withthe signal from the TESTER_ENABLE pin 23 a inverted at the input to theAND gate 25. The output of the first gate 25 is taken via a control line24 to the tristate output buffers 5 and controls their state. At thesame time, the signal from the TESTER_ENABLE pin 23 a is fed via anadditional, second gate 26 of the controller 28 with the signal from theSCAN_ENABLE pin 18 into the multiplexer 20, and hence into the ASIC core2. The second gate 26 is again an AND gate in the preferred exemplaryembodiment. This enables masking, that is blocking, of the signal fromthe SCAN_ENABLE pin 18 to the ASIC core 2 by means of the TESTER_ENABLEpin 23.

During the qualification test of the present invention, theunidirectional ASIC outputs are enabled. In order to prevent theSCAN_ENABLE signal from the pin 18 to the ASIC core 2 having any effectduring the qualification test, whether from PLLs or delay elements, theSCAN_ENABLE signal to the ASIC core 2 is blocked during thequalification test of the present invention, as explained above.

A pin TESTER_BIDIR 23 b is used as part of the controller 28 to controlthe at least one bidirectional pin 6 a. A signal at this pin 23 b isused to control whether the bidirectional pin 6 a is used as input oroutput pin. In a similar way to the TESTER_ENABLE pin 23 a, the signalfrom the TESTER_BIDIR pin 23 b is taken to a third gate 27 with anycontrol signals from the core 2 that may be present. In the preferredexemplary embodiment, the third gate 27 is an AND gate, and in a similarway to the first gate 25, the signal from the TESTER_BIDIR pin 23 b isinverted at the input to the gate. The output of the third gate 27controls the state of the bidirectional tristate output buffer 5 a viathe control line 29.

An explanation is given below as to how timing measurements, or what isknown as a core boundary scan, are made on the input areas and outputareas of the ASIC 1 by using the ASIC 1 described above.

A) Measuring the Clock-To-Output Time at the Output:

In order to measure the clock-to-output time, which is also known as theclock-to-output delay, the chain of input FFs 7 a, 7 b, 7 d with theoutput FFs 8 a, 8 b, 8 d, 8 c are brought into the shift mode by meansof the SCAN_ENABLE pin 18. The test vector, or the test pattern, for theoutputs is input serially via the TESTER_IN pin 3 c. The at least onebidirectional pin 6 a has been switched into the output mode via theTESTER_BIDIR pin 23 b. The clock-to-output time can be measured at theoutputs during the serial input sequence of the test vector, e.g. a 0101pattern. The measured times correspond to those when the ASIC 1 is innormal operation.

Thus, the test vector data is input serially at the input pin 3 c to thescan chain, or more precisely the shift register, and is analyzed inparallel at the output. It should be mentioned that a dedicated pin 3 cis not essential for the input, because certain inputs can be used inmore than one way.

B) Measurement of the Switching Speed:

The measurement of the switching speed of the tristate buffer 5 b of theat least one unidirectional pin 6 b from Z to 1, from Z to 0, from 0 toZ and from 1 to Z is provided by an additionally implemented flip-flop(FF) 8 d in the shift register. Control is effected via the test vectordata input serially at the input pin 3 c. Control signals from the flitflop 8 d or control signals from the gate 25 of the controller 28 arefed to the tristate buffer 5 b via a gate 30, which in the preferredexemplary embodiment is an OR gate.

The same effect can also be achieved for bidirectional pins by themeasure described.

C) Measurement of SETUP and HOLD Times at the Inputs:

When finding the SETUP and HOLD times, the at least one bidirectionalpin 6 a is switched to input via the TESTER_BIDIR pin 23 b. The inputFFs 7 a, 7 b, 7 d are in normal operation, i.e. operating in parallel.At the ASIC 1, the test vector pattern is applied to all input pins 3 a,3 b, 3 c for one clock pulse, and once the data has been transferredinto the input FFs 7 a, 7 b, 7 d, the shift mode is established via theSCAN_ENABLE pin 18 using the multiplexer 16 and the data is outputserially from the ASIC 1 so that the data can be analyzed.

This process is then repeated, but the step of applying the test inputpattern to all input pins 3 is varied in time relative to the clock.When the analyzed data contains errors, this is an indicator that theSETUP and HOLD timing criterion for the input FF or input FFs has beenviolated. Thus the SETUP and HOLD time can be found indirectly, becauseviolation of the timing at the inputs is signaled by erroneous output atthe outputs of the ASIC 1.

To sum up, it can be said that the present invention provides anelectronic component and a method for an improved timing measurement inintegrated circuits. The new component and the new method are based on asmall amount of advance hardware design work in the ASIC, generally alsoreferred to as Design for Test (DFT). The method and device describedabove provide the following advantages:

-   -   Only relatively short test vectors need to be used for the        timing measurement.    -   Short test times are obtained irrespective of the logic depth of        the ASIC 1 under test.    -   The test vectors can be generated automatically from a database        similar to the Boundary Scan Description Language file (BDSL        File).    -   The timing measurements can be performed without needing to put        the central core 11 into operation.    -   The clock tree 13 relevant to the test and the PLLs are included        in the timing measurements, i.e. a real clock is present during        the timing measurements.    -   Test teams need to get far less involved than before in the        function of the ASIC 1, thus reducing considerably the        preparation time involved in timing measurements.    -   The hardware overhead is low.

The present invention can also be used in particular in connection withthe International Application No. PCT/EP02/09690, filed Aug. 30, 2002,titled “Electronic component”, which is incorporated by reference hereinin its entirety.

1-22. (canceled)
 23. An electronic component with an integratedsemiconductor circuit, comprising: a core operatively connected to thesemiconductor circuit; a plurality of input flip-flops, connected toinput pins of the electronic component; a plurality of output flip-flopsconnected to output pins of the electronic component, wherein the inputflip-flops are interconnected to the output flip-flops to provide ashift register during a qualification test of the electronic component.24. The component as claimed in claim 23, wherein the input flip-flopsand the output flip-flops each have a switching element at their inputs,and are connected by the switching element, and are controlled by acontroller central to the switching elements.
 25. The component asclaimed in claim 23, wherein the input flip-flops and the outputflip-flops are each connected via input buffers to the input pins or viaoutput buffers to the output pins.
 26. The component as claimed in claim23, wherein the qualification test is a setup and/or hold measurement atthe input flip-flops.
 27. The component as claimed in claim 23, whereinthe qualification test is a clock-to-output time measurement at a outputflip-flop and/or an output of the component.
 28. The component asclaimed in claim 23, wherein the qualification test is anenable-to-output time measurement at a output flip-flop and/or an outputof the component.
 29. The component as claimed in claim 24, wherein theswitching elements are multiplexers.
 30. The component as claimed inclaim 24, wherein the switching element connects the output of an inputflip-flop or output flip-flop to the input of an adjacent inputflip-flop or output flip-flop during the qualification test.
 31. Thecomponent as claimed in claim 23, wherein all input and outputflip-flops receive the same clock via a clock tree.
 32. The component asclaimed in claim 23, wherein the input and/or output flip-flops receivea different clock via a clock tree.
 33. The component as claimed inclaim 24, wherein the controller comprises: a first pin for controllingthe switching elements; a second pin for controlling unidirectionaloutput buffers; and a third pin for controlling bidirectional outputbuffers.
 34. The component as claimed in claim 23, wherein thecontroller comprises a plurality of gates.
 35. A method forqualification testing of an electronic component having an integratedsemiconductor circuit, comprising: providing a core operativelyconnected to the semiconductor circuit; providing a plurality of inputflip-flops, connected to input pins of the electronic component;providing a plurality of output flip-flops connected to output pins ofthe electronic component; and connecting the input flip-flops and theoutput flip-flops into a shift register during a qualification test ofthe component.
 36. The method as claimed in claim 35, wherein the inputflip-flops and the output flip-flops each have a switching element attheir inputs, and are connected by the switching element, and arecontrolled by a controller central to the switching elements.
 37. Themethod as claimed in claim 35, further comprising: performing a setupand hold measurement of the input flip-flops as a qualification test.38. The method as claimed in claim 35, further comprising: parallellyinputting the test data into the input flip-flops via inputs of thecomponent; connecting the input flip-flops and the output flip-flopsinto the shift register by a controller; adapting test data passesserially through the shift register; and reading out the test data viaan output.
 39. The method as claimed in claim 35, wherein the setup andhold time is determined by varying a timing of the data input to theinput flip-flops relative to a clock and by verifying a test data readout.
 40. The method as claimed in claim 35, wherein a clock-to-outputtime measurement of the output flip-flops is performed as aqualification test.
 41. The method as claimed in claim 35, furthercomprising: connecting the input flip-flops and the output flip-flopsinto a shift register by a controller; serially shifting a test datainto an input flip-flop via an input of the component; serially passinga test data serially through the shift register; measuring theclock-to-output times at the outputs of the output flip-flops and/or atthe output pins during the shifting of the data into the outputflip-flops.
 42. The method as claimed in claim 35, further comprising:parallelly inputting a test data into the input flip-flops via theinputs of the component; connecting the input flip-flops and the outputflip-flops into a shift register by a controller; adapting the test datato reach the output flip-flops serially by passing through the shiftregister; and measuring the clock-to-output times at the relevantoutputs of the component during the shifting of the data into the outputflip-flops.
 43. The method as claimed in claim 35, wherein thequalification test is an enable-to-output time measurement of the outputflip-flops.
 44. The method as claimed in claim 35, further comprising:driving a tristate buffer by a flip-flop of a shift register during theenable-to-output time measurement of the output flip-flops, a testvector data serially input into the shift register being used forcontrol.